The proliferation of multicore processors and virtual processors has led to the increased use of virtual memory. Virtual memory provides the illusion of a contiguous section of memory to each process operating on the processors of a system, but the actual physical memory used by each process may be spread across a system's physical memory. In this regard, virtual memory is typically split into pages, with each page being mapped to a location of the system's physical memory. A page table may be used to map the virtual memory page of a piece of data to the corresponding physical address where the data is stored. In order to increase the speed of converting virtual memory pages to corresponding physical addresses, each core of a processor may implement a translation lookaside buffer (TLB) which stores recent translations of virtual memory pages to physical memory addresses.
When a virtual memory page mapping is modified in a page table, or when hypervisors unmap or otherwise modify a guest page from a virtual machine's virtual memory, the TLB for each processing core needs to be updated accordingly. In some scenarios this is accomplished by sending an interrupt, known as a TLB shootdown interrupt, which instructs each targeted processor core to review a software-defined list of unmapped virtual memory page entries, and to remove these entries from their respective TLB. The targeted processor cores may remove the unmapped entry from their respective TLB tables, and signal their completion to the initiating processor of the TLB shootdown. The OS software on the initiating processor must wait until all responses have returned before further processing may be resumed. Similarly, a receiving processor core must complete the TLB shootdown request before resuming further processing.
In a virtualized environment, sending and receiving interrupts, such as TLB shootdown requests, may be time-consuming as communication between physical processors and virtual processors requires the intervention of the hypervisor. Further, virtual processors may be offline (e.g., descheduled by the hypervisor or the physical CPU may be halted), thereby causing the TLB shootdown acknowledgement from those virtual processors to be delayed. In systems with a large number of virtual processors these delays may increase, sometimes super-linearly, resulting in significant performance reductions.